The present disclosure relates to a semiconductor device and a method for fabricating the same and specifically, to a semiconductor device including a gate electrode having a gate insulating film made of a high dielectric constant film and a metal film and to a method for fabricating the same.
A complementary metal-oxide semiconductor (CMOS) device is required to be further miniaturized. For miniaturization, it is necessary to reduce the thickness of a gate insulating film. However, when the thickness of a conventional, silicon oxide film-based gate insulating film is further reduced, a leak current increases, increasing a stand-by current of a large scale integration (LSI) circuit. Thus, the silicon oxide film-based gate insulating film has reached the limit of reducing the film thickness. Therefore, attention has been focused on a complementary metal-insulator semiconductor (CMIS) device in which instead of the silicon oxide film, an insulating film made of high dielectrics or the like is used as a gate insulating film. Since the electrical thickness of a high dielectric constant film can be reduced even when the physical thickness of the high dielectric constant film is increased, it is expected that the high dielectric constant film allows the thickness of the gate insulating film to be further reduced. Currently, hafnium silicate nitride (HfSiON) is regarded as the most promising high dielectric constant film for the gate insulating film.
Moreover, as to a gate electrode, depletion of a polysilicon electrode is no longer negligible. Therefore, a metal gate electrode without the depletion has been enthusiastically developed.
Meanwhile, in an n-type metal-insulator semiconductor field-effect transistor (MISFET) and a p-type MISFET, characteristics required for gate insulating films and gate electrodes are different. It is preferable that the n-type MISFET has a reduced work function and the p-type MISFET has an increased work function.
Therefore, the process of forming an n-type MISFET and a p-type MISFET having different gate insulating films and gate electrodes from each other has been proposed (for example, see S. C. Song et al., “Highly Manufacturable 45 nm LSTP CMOSFE Is Using Novel Dual High-k and Dual Metal Gate CMOS Integration”, VLSI, 2006, pp. 16-17).
In a method for fabricating the conventional semiconductor device, first, over a semiconductor substrate having a p-type region and an n-type region which are separate from each other by a device isolation region, a first insulating film and a first conductive film are sequentially formed. Subsequently, portions of the first insulating film and the first conductive film formed over the n-type region are selectively removed. Next, over the entire surface of the semiconductor substrate, a second insulating film and a second conductive film are sequentially formed. Subsequently, portions of the second insulating film and the second conductive film formed over the p-type region are selectively removed. Next, over the entire surface of the semiconductor substrate, a polysilicon film is formed. Then, the polysilicon film, the first conductive film, the second conductive film, the first insulating film, and the second insulating film are selectively removed. In this way, in the p-type region, a first gate electrode including the polysilicon film and the first conductive film and a first gate insulating film including the first insulating film are formed, and in the n-type region, a second gate electrode including the polysilicon film and the second conductive film and a second gate insulating film including the second insulating film are formed.
Making the first insulating film of HfSiON, the first conductive film of TiN, the second insulating film of HfO2, and the second conductive film of TaN can optimize the characteristics of the p-type MISFET and the n-type MISFET.